In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data are placed on a data bus by the memory device in synchronism with the external clock signal, and consequently, the memory device must provide the data to the bus at the proper times. To provide the data at the correct times, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the data onto the data bus. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully output the data at the proper times.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. Additionally, in the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
FIG. 1 is a simplified block diagram of output circuitry 100 for a conventional synchronous memory device, as well known in the art. The output circuitry 100 includes an output driver 102 that receives internal data signals DATA that represent binary data, and further receives a bidirectional data strobe signal DQS that is generated by a DQS generator 104. The DQS is eventually transmitted externally, along with data signals DQ, for use in the capture at a receiving device. The output circuitry 100 is coupled to a DLL 106 and trimmable delay 108 to receive a clock signal CLKDEL, and has an output coupled to an external data terminal of the memory device (not shown) in order to provide the data to a data bus. The DLL 106 generates a clock signal CLKDLL synchronized with an external clock signal CLK, which is applied to the DLL 106. The CLKDLL signal is then input to the trimmable delay 108 to generate the CLKDEL signal, which is a clock signal having a time delay tTRIM relative to the CLKDLL signal. In operation, the output driver 102 outputs the DQ and DQS signals in response a transition of the CLKDEL signal.
The trimmable delay 108 is included in the output circuitry 100 to take advantage of device performance exceeding the published timing specifications for the device, typically in order to increase internal timing margins. In conventional SDRAM devices, the time from when a read command is first latched by the memory device to when data is latched by the output driver 102 and ready to be output in response to the CLKDEL signal, is generally a fixed time that is inherent to the memory device. The time is typically referenced as tAA. Another timing characteristic inherent to a memory device, which will be referenced herein as tOUT, is the time from when a transition of the CLKDEL signal is detected by the output driver 102 and when the DQ and DQS are made available at the external terminal for reading. A common timing specification related to tOUT is tAC, which is defined as the access window of the DQ relative to a transition of the external CLK signal. That is, valid DQ is guaranteed to be present at the external data terminal no later than tAC after a transition of the CLK signal. As generally known in the art, the actual performance of the memory device, as measured by tOUT, exceeds the published performance, which is guaranteed to be no longer than tAC.
As previously mentioned, where the performance of the memory device exceeds the published timing specifications of the memory device, internal timing margins for the memory device can be improved. One approach is to use internal delays, such as the trimmable delay 108, to increase timing margins for related internal timing parameters. In the specific case of data output circuitry, such as the output circuitry 100, the excess performance of the memory device provided by tOUT over the published performance specification of tAC is often taken advantage of to increase the timing margin for tAA. The trimmable delay 108 is trimmed to set the time delay tTRIM for the CLKDEL signal relative to the CLKDLL signal. With more time delay tTRIM, the margin for tAA is increased. That is, the time for data to be provided to the output driver 102 after a read command is registered is increased. For example, with respect to FIG. 2, tTRIM is shown at the maximum time delay which the trimmable delay 108 can have and still meet the published tAC specification. The time tAA MARGIN represents additional time the DATA signal can take to be valid at the input of the output driver 102. Thus, the time for data to be provided to the output driver 102 following the receipt of a read command is increased, providing a greater range of tAAs that will yield memory devices which meet the published tAC performance specifications. The trimmed memory devices are then sorted for “speed-grades” based on the actual performance resulting from the trimming of the trimmable delay 108, as well known.
Although DLLs are assumed to be stable and frequency independent, in many designs the DLL has a delay component that varies with the frequency of the input clock signal. For example, the delay of a DLL may be proportionate with clock frequency, resulting in an output clock signal, which ideally is synchronized with the input clock signal, that increasingly lags the input clock signal as the frequency of the input clock signal increases. In applications in memory devices that can operate at different clock frequencies, which many conventional memory devices can do, the varying delay introduced by a non-ideal DLL will affect the timing of internal circuitry that relies on the clock signal generated by the DLL. With respect to the output circuitry 100, the varying delay of the DLL 106 will ultimately affect the timing of when the DQ and DQS signals will be output by the data driver 102. For memory devices operating at higher frequencies, unless the skew added by the DLL 106 is accommodated, the memory device may fail to meet published timing specifications.
Further complicating the timing restrictions of a memory device is that memory devices that can operate at different clock frequencies have CAS (read) latency restrictions for operations at the various external clock frequencies, as well known. CAS latency is typically defined as the delay, in number of clock cycles, between the registration of a read command and the availability of the first bit of output data. Generally, CAS latency is a lower value for lower external clock frequencies (e.g., a CAS latency value of 2 for an external clock frequency of 133 MHz) and a higher value for higher external clock frequencies (e.g., a CAS latency value of 3 for an external clock frequency of 200 MHz). In this manner, the total time which a memory device has to complete a read operation can be maintained, to some extent, for operation at the different clock frequencies.
Typically, the varying delay introduced by the DLL 106 is accommodated by setting the delay of the trimmable delay 108 based on a “worst-case” timing scenario that still meets published timing specifications. That is, assuming that the DLL 106 introduces a delay that varies as described above, the delay of the trimmable delay 108 is set assuming the memory device is operated at the highest published clock frequency and having the shortest tAC specification. More specifically, in order for the memory device to still meet the shortest published tAC when operated at the highest published clock frequency, the delay of the trimmable delay 108 must be reduced to compensate for the increasing delay of the non-ideal DLL 106. However, as a result of reducing the delay time of the trimmable delay 108, the overall timing margin for tAA is decreased. Where the memory device is operated at a lower maximum operating clock frequency, such as for memory devices categorized in slower speed-grades, the margin is further decreased because the time delay introduced by the DLL 106 is less for lower external clock frequencies. As previously discussed, having greater tAA margin can have a positive affect on the yield of memory devices that meet published timing parameters. By decreasing the delay of the trimmable delay 108, memory devices that would have otherwise been acceptable under a more relaxed tAA requirement may now no longer meet the published timing specifications because of the shorter delay of the trimmable delay 108. Consequently, the yield of acceptable memory devices can be negatively affected by setting the trimmable delay 108 to a shorter delay time.
The relationship between the previously discussed internal timing for the various signals is illustrated in FIGS. 2B and 2C. In FIG. 2B, at a time T0, the CLK signal has a positive signal transition from LOW to HIGH. At a time T1, a time delay tDLL1 after the time T0, the CLKDLL signal makes a positive transition in response to the CLK signal. The time delay tDLL1 represents the time delay of the non-ideal DLL 106 at the highest published operating frequency, which represents the worst-case timing scenario. At a time T2, the CLKDEL signal has a positive transition due to the set time delay tTRIM, which is set to the delay of the DLL 106 assuming the highest external clock frequency. In response to the transition of the CLKDEL signal at the time T2, the output driver 102 begins to output the DQ and DQS signals. However, as shown in FIG. 2B, a valid DATA signal is not provided to the output driver until a time T3, which is after the output driver 102 begins to output the DQ and DQS signals. Consequently, the information of the DQ signal output by the output driver 102 at a time T4 is unknown, and is considered invalid.
Categorizing the same memory device at a slower speed-grade (i.e., having lower maximum operating frequency and relaxed tAC) also does not result in a memory device meeting the published specifications, as illustrated by FIG. 2C. At a time T0, the CLK signal has a positive signal transition. In response, the CLKDLL signal has a positive transition a time delay tDLL2 later at a time T1. The time delay tDLL2 is less than the time delay tDLL1 shown in FIG. 2B because of the non-ideal characteristic of the DLL 106. More specifically, the time delay tDLL2 is less than the time delay tDLL1 because of the lower maximum operating clock frequency for the memory device having a slower speed-grade. At a time T2, a time delay tTRIM after the time T1, the CLKDEL signal has a transition, which causes the output driver 102 to begin outputting the DQ and DQS signal. The time delay tTRIM is the same as for FIG. 2B because, as previously mentioned, the time delay tTRIM is set based on the worst-case timing scenario, regardless of the speed-grade of the memory device. At the time T2, valid DATA is still not present at the input of the output driver 102, and consequently, the DQ and DQS signals output by the output driver 102 at a time T3 are unknown, and considered invalid. It is not until at a time T4, valid DATA reaches the input of the output driver 102.
As illustrated by the timing diagrams of FIGS. 2A and 2B, in some cases, the tAA margin may actually be reduced at a lower clock frequency for a memory device categorized in a slower speed-grade, although the tAC specification is more relaxed. Accommodating the two competing timing parameters, that is, having acceptable tAA margin versus meeting published tAC specifications for the highest clock frequency conditions, results in a compromise that attempts to minimize any negative affect to memory device yield. However, as well known, it is desirable to increase the yield of acceptable memory devices in order to reduce the manufacturing costs per memory device. Therefore, there is a need for an alternative approach to dealing with the tension between the inversely related timing parameters, and which can consequently have a positive effect on memory device yield.